1. Technical Field
The present invention relates to a data output clock generating circuit and a method of generating a data output clock of a semiconductor memory apparatus. In particular, the present invention relates to a data output clock generating circuit for a semiconductor memory apparatus, which can stably generate a data output clock to be used for data output in a semiconductor memory apparatus, and to a method of generating a data output clock for a semiconductor memory apparatus.
2. Related Art
In general, a data input/output operation of an SDRAM (Synchronous Dynamic RAM) is performed in synchronization with a rising edge of a clock. However, in a DDR SDRAM (Double Data Rate SDRAM), a data input/output operation is performed in synchronization with a rising edge and a falling edge of a clock using an internal DLL (Delay Locked Loop) circuit. Accordingly, the DDR SDRAM has a data input/output speed twice as large as the SDRAM. Therefore, a high-speed semiconductor memory apparatus such as the DDR SDRAM generates a clock (hereinafter, referred to as ‘rising clock’), which is enabled at the time of a rising edge of the clock output from the DLL circuit, and a clock (hereinafter, referred to as ‘falling clock’), which is enabled at the time of a falling edge of the clock output from the DLL circuit, for data output during a read operation. At this time, a data output clock generator generates a rising data output clock and a falling data output clock using an output enable signal, together with the rising clock and the falling clock, and transmits the generated rising data output clock and the generated falling data output clock to data output buffers, such that a data output operation is performed.
A data output clock generating circuit according to the related art will now be described with reference to FIGS. 1 to 3.
FIG. 1 is a block diagram illustrating a data output process of a general semiconductor memory apparatus. In this example the semiconductor memory apparatus has 16 data output buffers.
Referring to FIG. 1, an output enable signal generator 10 generates a rising output enable signal roe and a falling output enable signal foe. A data output clock generator 20 receives the rising output enable signal roe and the falling output enable signal foe, together with a rising clock rclk and a falling clock fclk transmitted from a DLL circuit and generates a rising data output clock rclk_do and a falling data output clock fclk_do. Sixteen data output buffers 30 individually receive the rising data output clock rclk_do and the falling data output clock fclk_do output from the data output clock generator 20, and perform the data output operation. The number of the data output buffers 30 differs between semiconductor memory apparatuses, and is not limited to the configuration shown in the drawing.
In order to output data at the time of the rising edge of the DLL clock, the output enable signal generator 10 generates the rising output enable signal roe, which is changed in synchronization with the falling clock fclk, and transmits the generated rising output enable signal roe to the data output clock generator 20. Then, the data output clock generator 20 generates the rising data output clock rclk_do from the rising clock rclk transmitted from the DLL circuit and the rising output enable signal roe, and transmits the generated rising data output clock rclk_do to the 16 data output buffers 30. Each of the data output buffers 30 outputs rising data by the number of bits corresponding to the length of the input rising data output clock rclk_do.
Similarly, in order to output data at the time of the falling edge of the DLL clock, the output enable signal generator 10 generates the falling output enable signal foe, which is changed in synchronization with the rising clock rclk, and transmits the generated falling output enable signal foe to the data output clock generator 20. Then, the data output clock generator 20 generates the falling data output clock fclk_do from the falling clock fclk transmitted from the DLL circuit and the falling output enable signal foe, and transmits the generated falling data output clock fclk_do to the 16 data output buffers 30. Each of the data output buffers 30 outputs falling data by the number of bits corresponding to the length of the input falling data output clock fclk_do.
FIG. 2 is a diagram showing the internal configuration of the clock generator shown in FIG. 1.
As shown in FIG. 2, the data output clock generator 20 has a rising data output clock generating unit 210 which receives the rising output enable signal roe and the rising clock rclk and generates the rising data output clock rclk_do, and a falling data output clock generating unit 220 which receives the falling output enable signal foe and the falling clock fclk and generates the falling data output clock fclk_do.
The rising data output clock generating unit 210 and the falling data output clock generating unit 220 each have a NAND gate 212, 222 and an inverter 214, 224.
With this configuration, in the rising data output clock generating unit 210, when the rising output enable signal roe is enabled, the input rising clock rclk is output as the rising data output clock rclk_do. Similarly, in the falling data output clock generating unit 220, when the falling output enable signal foe is enabled, the input falling clock fclk is output as the falling data output clock fclk_do.
FIG. 3 is a timing diagram illustrating a data output process of the semiconductor memory apparatus according to the related art. In FIG. 3, for example, 8-bit data is output by the data output clock.
Referring to FIG. 3, it should be understood that the rising clock rclk is generated at the time of the rising edge of the DLL clock dll_clk and the falling clock fclk is generated at the time of the falling edge of the DLL clock dll_clk. Furthermore, it can be understood that the falling output enable signal foe is generated by the rising clock rclk, and the rising output enable signal roe is generated by the falling clock fclk. The rising data output clock rclk_do is the rising clock rclk extracted when the rising output enable signal roe is enabled. Similarly, the falling data output clock fclk_do is the falling clock fclk extracted when the falling output enable signal foe is enabled.
In a low-speed semiconductor memory apparatus, the generation of the data output clocks rclk_do and fclk_do according to the above-described configuration does not cause any problems. In a high-speed semiconductor memory apparatus, however, as the frequency of the DLL clock dll_clk becomes high, a timing margin between the rising output enable signal roe and the rising clock rclk, and a timing margin between the falling output enable signal foe and the falling clock-fclk are decreased. In order to output 8-bit data, the rising data output clock rclk_do and the falling data output clock flck_do need to have four cycles. Accordingly, the rising output enable signal roe and the falling output enable signal foe need to be enabled in a period of four or more cycles of the rising clock rclk and the falling clock fclk, respectively. However, if the enable periods of the rising output enable signal roe and the falling output enable signal foe are decreased due to the decrease in the timing margin, a data output clock clk do may not have four cycles, and thus 8-bit data may be not obtained. That is, in the high-speed semiconductor memory apparatus, the rising data output clock rclk_do and the falling data output clock fclk_do may be improper due to the decrease in the timing margin between the rising output enable signal roe and the rising clock rclk and between the falling output enable signal foe and the falling clock fclk. Accordingly, an erroneous data output operation may occur.